This invention relates generally to semiconductors and more particularly to complementary metal-oxide-semiconductor (CMOS) transistors.
As is known in the art, CMOS transistors are include of a pair (one n-type and one p-type) of metal-oxide-semiconductor field effect transistors (MOSFETS). MOSFETS are fabricated by diffusing two, spaced n-type regions (known as the source and the drain) into a p-type substrate or by diffusing two, spaced p-type regions into an n-type substrate, producing an n-channel MOSFET or a p-channel MOSFET respectively. In addition, a metal gate electrode is disposed over the substrate region separating the source and drain and is insulated therefrom by a layer of insulating material such as an oxide which is generally principally comprised of silicon dioxide.
For an n-channel metal-oxide semiconductor (NMOS) device, when a positive voltage is applied to the gate, the field from the gate will draw electrons into the substrate region surrounding the gate causing a channel to be formed between the drain and source. This formed or induced channel allows current to flow between the source and drain electrodes of the transistor. With a gate voltage present, an increase in drain to source voltage will result in an increase in drain current. As the drain to source voltage continues to increase, the electric field produced under the gate increases.
As is also known, it is desirable to provide increasing numbers of transistors on an integrated circuit (IC) chip without increasing the overall size of the IC chip. One technique to increase circuit density is to scale down the size of each individual transistor on a IC chip. While scaling provides smaller devices and which can be more densely packed, there are several problems associated with scaling.
Although the transistors have been reduced in size, the computer systems in which they are employed typically maintain the same supply voltage levels (e.g. 5 volts). If the supply (or drain) voltage remains constant while the size of the transistor decreases, there is an adverse effect on the current supplying capability of the transistors due to a so called "hot carrier" effect.
In particular, when a MOS type transistor is reduced in size, the distance between the two diffused regions becomes smaller. The field produced under the gate is inversely related to the distance between the diffused regions. A reduction in the distance between the diffused regions without a corresponding decrease in the supply voltage will cause a dramatic increase in the size of the field produced under the gate.
Increasing the size of the field causes the electrons and holes flowing beneath the gate to become excited and accelerate or become "hot". The acceleration of carriers due to an increased field is known as the so called "hot carrier" effect. As the field increases in magnitude the hot carrier effect correspondingly increases and carriers can become so excited that they cross over the substrate/oxide interface and become trapped in the barrier oxide near the interface which separates the gate from the underlying substrate. In addition or instead of becoming trapped, the hot carriers can cause damage to the interface in the form of so called "interface states". These trapped carriers or interface states are undesirable because they modify the current carrying capability of the transistors. The presence of this charge in the barrier oxide at the interface tends to repel the normal current flow in a portion of the channel underlying the gate. Therefore current flow is impeded resulting in less drain current and therefore a slower circuit.
It is well know that introducing nitrogen into the barrier oxide results in an increased resistance to hot carriers crossing into the barrier oxide as compared to the standard gate oxides. Gate oxide nitridation has been accomplished using various methods such as nitridation using NH.sub.3, N.sub.2 O oxidation, and N.sub.2 implantation into polysilicon followed by a high temperature anneal. Several problems exist with each of these techniques.
Nitridation in NH.sub.3 is a process wherein a pre-existing oxide undergoes a high temperature anneal in an ambient environment of NH.sub.3. This method of nitrogen incorporation yields nitrogen concentrations of up to 1.times.10.sup.12 /cm.sup.2 at the substrate/oxide interface. However, this method of nitridation adversely affects the PMOS (p-type MOSFET) transistor performance by introducing a large amount of hydrogen into the gate oxide. Having a large amount of hydrogen in the gate oxide results in negative bias temperature instability (NBTI) and therefore a less reliable transistor.
Oxidation of Si in N.sub.2 O is a hydrogen free process wherein the nitridation occurs as the gate oxide is grown. Since the process is hydrogen free, the NBTI problem is eliminated. However, N.sub.2 O oxidation results in low nitrogen content, typically in the range of 8.times.10.sup.10 /cm.sup.2 to 2.times.10.sup.11 /cm.sup.2, at the SiO.sub.2 /S.sub.i interface compared to the levels achieved using the NH.sub.3 process described above.
Nitrogen implantation into polysilicon is a process wherein a high dose (typically greater than 1.times.10.sup.16 /cm.sup.2) of nitrogen is implanted into polysilicon followed by a 1100.degree. C. annealing step. Polysilicon is a polycrystalline solid comprised of many small regions of single-crystal material whereas silicon is a crystalline solid wherein the atoms are arranged in a periodic fashion. However, here again the interfacial nitrogen content at the SiO.sub.2 /Si interface is limited by mechanisms of nitrogen diffusion and solubility in the-polysilicon/SiO.sub.2 /Si multi-layer system with typical concentration levels being approximately 4.times.10.sup.11 /cm.sup.2. Due to the interplay of these mechanisms, the process is extremely difficult to control. Additionally, if a larger amount of nitrogen is required at the interface, the nitrogen dose in polysilicon must be increased which can result in the formation of an insulating layer of Si.sub.3 N.sub.4 within the poly which is detrimental to transistor operation. Lastly, the high temperature annealing step required to drive the implanted nitrogen to the SiO.sub.2 /Si interface is not compatible with CMOS VLSI processing.